5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO

Description

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS10 kHz to 20 MHz integration bandwidth.. It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS).

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Features

• Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter.
• Fully Configurable Outputs Including Frequency, Output Format, and Output Skew.
• Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs.
• Multiple Operational Modes Include Clock Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Holdover Mode
• Integrated EEPROM Determines Device Configuration at Power-up
• Excellent Jitter Performance
• Integrated Frequency Synthesizer including PLL, Multiple VCOs, and Loop Filter:
  • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode.
  • Programmable Charge Pump Gain and Loop Filter Settings
  • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz–2.356 GHz
• Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or Combinations of Differential or Single-ended:
  • 0.35 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
  • Low Output Phase Noise: –130 dBc/Hz at 1 MHz offset, F_c = 491.52 MHz
  • Output Frequency Ranges From 4.25 MHz to 1.175 GHz in Synthesizer Mode
  • Output Frequency up to 1.5 GHz in Fan-out Mode
  • LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
  • Independent Output Dividers Support Divide Ratios from 1–80, Non-continuous values supported.
  • Independent Coarse Skew Control on all Outputs, The coarse skew control does not operate for reference input frequencies less than 1 MHz
• Flexible Inputs With Innovative Smart Multiplexer Feature:
  • Two Universal Differential Inputs Accept Frequencies in the Range of 40 kHz to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS).

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