High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO

Description

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O:

• VC(X)O_IN / PRI_REF = (N x P) / M or
• VC(X)O_IN / SEC_REF = (N x P) / M

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy.

View full Description in Datasheet

Features

• High Performance LVPECL and LVCMOS PLL Clock Synchronizer
• Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
• Accepts LVCMOS Input Frequencies Up to 200 MHz
• VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
• VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
• Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs)
• Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually
• Efficient Jitter Cleaning From Low PLL Loop Bandwidth
• Low Phase Noise PLL Core
• Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
• Wide Charge Pump Current Range From 200 µA to 3 mA
• Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
• Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
• Analog and Digital PLL Lock Indication
• Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
• Frequency Hold-Over Mode Improves Fail-Safe Operation
• Power-Up Control Forces LVPECL Outputs to 3-State at V_CC < 1.5 V
• SPI Controllable Device Setting
• 3.3-V Power Supply
• Packaged in 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)

View All Features in Datasheet